IEEE

Reversible Full Adder/Subtractor

Abstract: This paper proposes two novel designs of Adder/Subtractor using reversible logic gates. The first design is an implementation of two's complement Adder/Subtractor suitable for ...
Nature

Implementation of half adder and half subtractor with a simple and universal DNA-based platform

As a powerful material, DNA presents great advantages in the fabrication of molecular devices and higher-order logic circuits. Herein, by making use of the hybridization and displacement of DNA ...
IEEE

A novel approach for reversible realization of 8-bit adder-subtractor circuit with optimized quantum cost

Abstract: Low power efficient digital devices are target of researchers in recent years. This aim attracted researchers to focus on the reversible digital circuit design approach. In ideal situations ...
GitHub

Parametrized Verilog implementation of different architectures of adder / subtractor circuits.

All the implemented adders are parametrized using the following parameters. Parameter Definition Default Value DATA_WIDTH The size of the two operands being added. 16 BLOCK_SIZE This parameter is used ...